Charge pumps develop a voltage by adding or removing charge from a load, such as a capacitor. Adding charge to the capacitor increases the voltage across the capacitor, and removing charge decreases the voltage. Charge pumps are used in a variety of applications, such as to produce a control voltage used to tune a voltage-controlled oscillator (“VCO”) in a phase-locked loop (“PLL”). In particular applications, a charge pump is included in a PLL of a digital clock manager (“DCM”), which is also known as a clock management tile (“CMT”).
FIG. 1 is a diagram of a conventional charge pump 100. Current sources 102, 104 are selectively coupled to the output or load 106, which in this case is illustrated as a capacitor for purpose of convenient example and discussion, to add or remove charge. The load develops an output voltage VOUT 120, such as VC in a PLL that is used to control a VCO or other circuit, in which case VOUT is commonly referred to as a “control voltage” or a “filter voltage.” A VCO/PLL is used only for purposes of convenient illustration. Charge pumps are used in a wide variety of applications.
The first current source 102 is commonly referred to as the “UP” current source because, when switch 108 is closed and switch 110 is open, charge is added to the load 106, increasing VOUT. The second current source 104 is commonly referred to as the “DOWN” current source because when switch 110 is closed and switch 108 is open, charge is removed from the load 106, decreasing VOUT. The terms “UP” and “DOWN” are arbitrary, as are the polarities of the circuit elements. In other words, whether the charge added and removed from the load is positive or negative, and whether the voltage developed across the load is positive or negative, is arbitrary. The UP current sources are connected directly to VCC or a regulated supply, for example.
The control voltage VOUT 120 is provided to a PLL (not shown) to control a VCO. A phase/frequency detector 112 provides control signals 114, 116 indicating whether the control voltage VOUT needs to change in order to tune the VCO to the proper phase or frequency. If the phase/frequency detector indicates that VOUT needs to be increased, the control signal 114 closes the UP switch 108 to transfer additional charge to the load 106. If the phase/frequency detector indicates that VOUT needs to be decreased, the control signal 116 closes the DOWN switch 110 to remove charge from the load 106. Only one of the switches 108, 110 is closed at any time and both switches are open if no adjustment to VOUT is required. However, in some applications, a technique is used that closes both switches 108, 110 for a short time during an UP or DOWN adjustment. This is done to cancel-out any non-ideal behavior of the switch that otherwise might lead to static phase offset.
The amount of charge added to or removed from the load 106 is determined according to the current of the current sources 102, 104 and the duration its corresponding switch is closed. In other words, one can determine the amount of charge added to the load 106 by knowing the current provided by UP current source 102 and the time UP switch 108 is closed. VOUT 120 is usually coupled to a high-impedance load, and it is typically assumed that essentially all of the charge is transferred to the load 106. However, even if there is some leakage through the output 120 or through the load 106, this would de-tune the VCO and result in the appropriate control signal being sent to re-tune the VCO to its desired frequency.
In typical applications, it is desirable that the charge added by an UP control signal is equal to the charge removed by a DOWN control signal because this leads to symmetric behavior of the PLL to both DOWN and UP adjustments. Additionally, the technique used to cancel-out non-ideal switch behavior by closing both switches for some amount of time relies on the fact that if both switches 108, 110 are closed, the currents will be canceled out and no net charge will be transferred to the load. Any offset between the UP and DOWN currents (i.e. the current provided by the UP current source 302 and the DOWN current source, respectively) will result in a net positive or negative charge being placed on the load when both switches 108, 110 are closed. This net charge will result in increased static phase offset.
When no change to the VCO is required, no control signal (i.e. an UP pulse or a DOWN pulse) is sent, or the charge pump is sent alternating UP and DOWN control signals. If the amount of charge transferred during a UP increment does not equal the amount of charge transferred during a DOWN increment, static phase error arises. It is highly desirable that the UP and DOWN control signals have the same duration, and that the UP and DOWN current sources provide the same current, since this greatly simplifies operation of the charge pump 100.
The charge pump 100 includes a current mirror section 122 that equalizes the UP and DOWN currents at a voltage level, which is a selected design parameter of the current mirror section 122. A voltage reference (not shown), such as a band-gap reference, is coupled to the DOWN current bias port 124. The voltage reference sets the operating point for a DOWN current mirror source 126 and for the DOWN current source 104. The current through the DOWN mirror current source 126 also depends on the voltage drop from node 128 to ground 130. In a particular embodiment, the voltage reference is coupled to the gate terminal of an FET, node 128 is coupled to the source of the FET, and the drain of the FET is coupled to ground 130.
The voltage at node 128 is typically greater than a transistor threshold voltage lower than the supply voltage VCC 132 provided to an UP mirror current source 134 and to the UP current source 102. In a particular embodiment, the UP mirror current source is diode-connected, allowing the voltage on node 128 to adjust itself to the correct bias point to supply the same current as the DOWN current source. The final voltage at node 128 is not only design-dependent but will also vary with process, voltage and temperature. The two current sources in the current mirror 134, 126 are replicated in the charge pump 102, 104 and may employ a multiplication factor.
If the output voltage, VOUT 120, is the same as the voltage on node 128, the currents will match, disregarding any device mismatch. However, as the output voltage level VOUT moves away from the voltage level of node 128, the difference between the UP current and the DOWN current increases due to the output impedance of the current sources, particularly in low-voltage circuits that use non-cascaded, single-transistor current sources.
One approach to minimize the difference between UP and DOWN currents is to use cascaded current sources, which increases the output impedance. This approach is not effective in low-voltage (e.g. about 1 Volt) circuits because there is not sufficient voltage headroom to provide cascaded current sources and still obtain the desired range of output voltage VOUT. One result is that some charge pumps used in low-voltage circuits produce an undesirable mismatch between the UP and DOWN currents versus output voltage VOUT.
Therefore, techniques for avoiding differences in UP and DOWN current in charge pumps are desired.